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CY244/45ZXC
Factory Programmable Quad PLL Clock Generator with VCXO
Features
* Fully integrated phase-locked loops (PLLs) * Selectable Output Frequency * Programmable Output Frequencies * Output Frequency Range of 5-166 MHz * Input Frequency Range -- Crystal: 10-30 MHz -- External Reference: 1-100 MHz * Analog VCXO * 16-/20-pin TSSOP packages * 3.3V operation
Benefits
* Meets most Digital Set Top Box, DVD Recorder and DTV application requirements * Multiple high-performance PLLs allow synthesis of unrelated frequencies * Integration eliminates the need for external loop filter components * Meets critical timing requirements in complex system designs * Enables application compatibility * Complete VCXO solution with 120 ppm (minimum pull range)
Block Diagram
CLKA
CLKB PLL1 XIN XOUT VIN VCXO PLL2 Divider & Multiplexer PLL3 CLKC
CLKD
CLKE
CLKF PLL4 CLKG
FS0/1/2 OE
Select Logic
Pin Configuration
16-Pin TSSOP
XIN AVDD VIN AVSS CLKA/OE VSS CLKB FS1 1 2 3 4 16 15 14 XOUT VDD CLKG CLKF VSS VDD FS0 CLKC
XIN FS2 AVDD VIN AVSS OE/PD CLKA VSS CLKB FS1
20-Pin TSSOP
1 2 3 4 5 20 19 18 17 XOU T VDD CLKG CLKF VSS CLKE CLKD VDD FS0 CLKC
13 CY244ZXC 5 12 6 7 8 11 10 9
16 CY245ZXC 6 15 7 8 9 10 14 13 12 11
Cypress Semiconductor Corporation Document #: 38-07748 Rev. **
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised March 7, 2005
CY244/45ZXC
Pin Description
Pin Number Pin Name XIN XOUT CLKA CLKB CLKC CLKD CLKE CLKF CLKG FS0 FS1 FS2 OE/PD VIN VDD VSS AVDD AVSS 16-pin TSSOP 1 16 5[1] 7 9 N/A N/A 13 14 10 8 N/A 5[1] 3 11,15 6,12 2 4 20-pin TSSOP 1 20 7 9 11 14 15 17 18 12 10 2 6 4 13,19 8,16 3 5 Pin Description Crystal Input or Reference Clock Input Crystal Output (No connect if external clock is used) Clock Output Clock Output Clock Output Clock Output Clock Output Clock Output Clock Output Frequency Select 0 Frequency Select 1 Frequency Select 2 Output Enable Control/Power Down Analog Control Input for VCXO Voltage Supply Ground Analog Voltage Supply Analog Ground crystal. Generally a design may require up to 4 oscillators to accomplish what could be done with a single CY24xZXC. Each PLL is independent and can be configured to generate a VCO (Voltage Controlled Oscillator) frequency between 62.5 MHz and 250 MHz. Each PLL can then in turn be divided down with post dividers to generate the clock output frequency of the user's choice. The output divider allows each clock output to be divided by 1,2,3,4,6,8,9,10,12,15. The PLL maximum is reduced to 166 MHz in divide by 1 mode due to output buffer limitations. Outputs that allow frequency switching perform the transition free of glitches. A glitch is defined as a high or low time shorter than half the smaller of the two periods being switched between. Extended low time (even many cycles in duration) is acceptable. Please refer to Figure 5. In order to minimize PPM (Parts Per Million) error on the clock outputs, a user should try and choose a crystal reference frequency that is a common multiple of the desired PLL frequencies. While this would be the ideal situation, this is not always the case and the PLLs have high resolution counters internally to help minimize frequency deviation from the desired frequency. PLL VCO frequencies are generated by the following equation: FVCO = FREF * (P / Q) Where FREF is the reference input frequency, P is the PLL feedback divider and Q is the reference input divider. A PLL is a feedback system where the VCO frequency divided by P and reference frequency divided by Q are constantly being compared and the VCO frequency is adjusted to achieve a locked state. Figure 1 is a simplified drawing of a PLL.
General Description
The CY24xZXC family of devices has an Analog VCXO (Voltage Controlled Crystal Oscillator), 4 PLLs, up to 7 clock outputs, and frequency selection capabilities. The frequency selects do not modify any PLL frequency. Instead, they allow the user to choose between up to 8 different output divider selections depending on the clock and package configuration. This is illustrated in Frequency Selection tables 1 and 2. There is one programmable OE/PDWN. The OE/PDWN pin can be programmed as either an output enable pin or a power down pin. The OE function can be programmed to disable a selected set of outputs when low, leaving the remaining outputs running. Full chip power-down will disable all outputs as well as the PLLs and most of the active circuitry when low. Factory-Programmable CY24xZXC Factory programming is available for high or low volume manufacturing by Cypress. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. Once the request has been processed, you will receive a new part number, samples, and data sheet with the programmed values. This part number will be used for additional sample requests and production orders. Please refer to the CY223388/89/91 data sheet for up to 8 clock outputs and compatibility with most SMD type crystals.
PLLs
The advantage of having 4 PLLs is that a single device can generate up to 4 independent frequencies from a single
Note: 1. Pin 5 16-pin TSSOP (choice between clock output or OE/PD)
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CY244/45ZXC
FR E F
/Q
V C O a nd
O t her c o m pon ent s
F V CO
The third mode disables the VCXO input control and sets the internal oscillator to a fixed frequency operation. The load capacitance seen by the external crystal when connected to pins XIN and XOUT is typically equal to 10pF. One of the key components to the CY24xZXC family of devices is the analog VCXO. The VCXO is used to "pull" the reference crystal higher or lower in order to lock the system frequency to an external source. This is ideal for applications where the output frequency needs to track along with an external reference frequency that is constantly shifting. The VCXO is completely analog, so there is infinite resolution on the VCXO pull curve. The Analog to Digital Converter steps that are normally associated with a digital VCXO input are not present in this device. A special pullable crystal must be used in order to have adequate VCXO pull range. Pullable Crystal specifications are included in this data sheet. Please contact the local Cypress Field Application Engineer (FAE) or sales representative for pullable crystal recommendations outside of the standard industry frequencies given in the Pullable Crystal Specifications.
/P
Figure 1. Simplified PLL
Frequency Select Pin Operation
Table 1. CY244ZXC 16-pin TSSOP Output Signal CLOCK B & CLOCK C CLOCK A & CLOCK F CLOCK G Frequency Selection Lines FS1 FS0 FS0 FIXED
Table 2. CY245ZXC 20-pin TSSOP Output Signal CLOCK C CLOCK B & CLOCK D CLOCK G Frequency Selection Lines FS2 FS1 FS0 FS1 FS0 FIXED
VCXO Profile
Figure 2 shows an example of what a VCXO profile looks like. The analog voltage input is on the X-axis and the PPM range is on the Y-axis. An increase in the VCXO input voltage results in a corresponding increase in the output frequency. This has the effect of moving the PPM from a negative to positive offset.
200 150
CLOCK A, CLOCK E, & CLOCK F FS0
Tuning [ppm
Analog VCXO
There are three programmable reference operating modes for the CY24xZXC family of devices. The first mode utilizes an external pullable crystal and incorporates an internal Analog VCXO. The second mode configures the internal crystal oscillator to accept an external driven reference source from 1 to 100 MHz. The input capacitance on the XIN pin when driven in this mode is typically 15pF.
100 50 0 -50 -100 -150 -200 VCXO input [V] 0 0.5 1 1.5 2 2.5 3 3.5
Figure 2. VCXO Profile
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CY244/45ZXC
Absolute Maximum Conditions
Parameter VIN TS ESDHBM UL-94 MSL Input Voltage Temperature, Storage ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level 16 and 20 pin TSSOP 1 Description Condition Relative to VSS Non-Functional MIL-STD-883, Method 3015 V-0 @1/8 in. Min. -0.5 -0.5 -65 2000 - Max. 4.6 VDD + 0.5 +125 - 10 Unit V VDC C Volts ppm VDD/AVDD/VDDL Core Supply Voltage
Pullable Crystal Specifications[2, 4]
Parameter FNOM CLNOM R1 DL C0[3] C1[3] F3SEPHI[4] F3SEPLO[4] C0/C1 Description 10 to 30 MHz Crystal AT-Cut Nominal load capacitance Equivalent series resistance (ESR) Crystal drive level Crystal shunt capacitance Crystal motional capacitance Third overtone separation from 3*FNOM Mechanical Third (High side of 3*FNOM) Third overtone separation from 3*FNOM Mechanical Third (Low side of 3*FNOM) Ratio of shunt to motional capacitance Comments Parallel resonance, Fundamental mode CLNOM =14 pF (0 ppm) Fundamental mode (CL = Series) No external series resistor assumed 13.5 - - - 14.4 380 - - Min. Typ. 14 - - - 18 - - - Max. 14.5 25 500 7 21.6 - -170 250 Unit pF W pF fF ppm ppm See Note 4
Recommended Operating Conditions
Parameter VDD/AVDD/VDDL Operating Voltage TA CLOAD tPU Ambient Temperature Maximum Load Capacitance Power-up time for all VDDs reach minimum specified voltage (power ramps must be monotonic) Description Min. 3.0 0 - 0.05 Typ. 3.3 - - - Max. 3.6 70 15 500 Unit V C pF ms
DC Parameters
Parameter IOH IIH IIL VIH VIL VVCXO CIN IVDD CINXIN Crystal Load
[5]
Description Output High Current Output Low Current Input High Current Input Low Current Input High Voltage Input Low Voltage VIN Input Range Input Capacitance Supply Current Input Capacitance at XIN Crystal Load Capacitance
Conditions VOH = VDD - 0.5, VDD = 3.3V VOL = 0.5, VDD = 3.3V VIH = VDD, excluding Vin, Xin VIL = 0V, excluding Vin, Xin FS0/1/2 OE input CMOS levels FS0/1/2 OE input CMOS levels FS0/1/2 and OE Pins only VDD/AVDD/VDDL Current VCXO Disabled External Reference VCXO Disabled Fixed Freq. Crystal
Min. - - - - 0.7xAVDD - 0 - - - -
Typ. 12 12 5 5 - - - - 85 15 10
Max. - - 10 10 - 0.3xAVDD AVDD 7 - - -
Unit mA mA A A V V V pF mA pF pF
IOL[5]
Notes: 2. Device operates to the following specs, which are guaranteed by design. 3. Increased tolerance available from pull range less than 120 ppm. 4. ECX-5953 Series crystal orderable from Ecliptek Corporation. Please refer to the CY22388/89/91 data sheet for compatibility with most SMD type crystals. 5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs.
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CY244/45ZXC
AC Parameters
Parameter[4] 1/t1 DC1[6] DC2 DCREFOUT ER EF T9[7] T10 fXO Description Output Frequency Output Duty Cycle Output Duty Cycle Reference Output Duty Cycle Rising Edge Rate Falling Edge Rate Clock Jitter PLL Lock Time VCXO Crystal Pull Range Conditions PLL minmax/Dividermaximum Duty Cycle is defined in Figure 3; t2/t1, 50% of VDD Duty Cycle is defined in Figure 3; t2/t1, 50% of VDD Duty Cycle is defined in Figure 3; t2/t1, 50% of VDD (XIN Duty Cycle = 45/55%) Output Clock Edge Rate. Measured from 20% to 80% of VDD. CLOAD = 15 pF. See Figure 4. Output Clock Edge Rate. Measured from 80% to 20% of VDD. CLOAD = 15pF See Figure 4. Period Jitter
External reference duty cycle between 40% and 60% measured at VDD/2 (Clock output is 125MHz)
Min. Typ. Max. Units 4.2 45 40 40 0.8 0.8 - - - 50 50 50 1.2 1.2 250 1 - 166 55 60 60 - - - 5 - MHz % % % V/ns V/ns ps ms ppm
External reference duty cycle between 40% and 60% measured at VDD/2 (Clock output is > 125MHz)
Using Crystal specified in "Pullable Crystal Specifications" table. 120 Nominal Crystal Frequency Input assumed (0ppm)@25C and 3.3V
Test and Measurement Set-up
V DDs DUT 0.1F Outputs C LOAD
GND
Voltage and Timing Definitions
t1 t2 V DD 50% of V DD Clock Output
Figure 3. Duty Cycle Definition
Note: 6. Excluding any output configured as a reference. 7. Jitter measurement will vary. Actually jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, and device programming.
0V
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CY244/45ZXC
t3 t4
V DD 80% of V DD 20% of V DD 0V
Clock Output
Figure 4. ER = (0.6 x VDD)/t3, EF = (0.6 x VDD)/t4 Finish Cycle Start at Full Cycle
FS
Figure 5. FS Controlled Clock Output
Ordering Information
Part Number[8] Lead-free Type Production Flow
CY244ZXC-XXX CY244ZXC-XXXT CY245ZXC-XXX CY245ZXC-XXXT
16-pin TSSOP 16-pin TSSOP - Tape and Reel 20-pin TSSOP 20-pin TSSOP - Tape and Reel
Commercial, 0C to +70C Commercial, 0C to +70C Commercial, 0C to +70C Commercial, 0C to +70C
Note: 8. The CY244ZXC-xxx, CY245ZXC-xxx are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative.
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CY244/45ZXC
Package Drawing and Dimensions
16-lead TSSOP 4.40 mm Body Z16.173
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
PACKAGE WEIGHT 0.05 gms PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG.
16
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008]
4.90[0.193] 5.10[0.200]
51-85091-*A
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CY244/45ZXC
Package Drawing and Dimensions (continued)
20-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z20
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN. MAX.
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
REFERENCE JEDEC MO-153 PART # Z20.173 STANDARD PKG. ZZ20.173 LEAD FREE PKG.
20
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX. GAUGE PLANE 0.076[0.003]
0.25[0.010] BSC 0-8
0.85[0.033] 0.95[0.037]
0.05[0.002] 0.15[0.006] 6.40[0.252] 6.60[0.260]
SEATING PLANE
0.50[0.020] 0.70[0.027]
0.09[[0.003] 0.20[0.008]
51-85118-*A
All product and company names mentioned in this document are trademarks of their respective holder.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY244/45ZXC
Document History Page
Document Title: CY244/45ZXC Factory Programmable Quad PLL Clock Generator with VCXO Document Number: 38-07748 REV. ECN NO. Issue Date Orig. of Change Description of Change
**
330814
See ECN
RGL
New data sheet
Document #: 38-07748 Rev. **
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